CoolRunner-II器件使用施密特觸發(fā)器
發(fā)布時間:2008/9/17 0:00:00 訪問次數(shù):686
coolrunner-ii器件中的每個輸入/輸出腳都具有施密特觸發(fā)器(schmitt trigger)的功能,并可提供500 mv的磁滯范圍。該功能除了能夠有效地抑制噪聲和用于模擬信號的接收之外,還可用于rc振蕩回路,為系統(tǒng)提供靈活和廉價的時鐘信號。該功能可以通過屬性控制來使能和旁路。
(1)約束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl語言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog語言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
歡迎轉(zhuǎn)載,信息來自維庫電子市場網(wǎng)(www.dzsc.com)
(1)約束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl語言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog語言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
歡迎轉(zhuǎn)載,信息來自維庫電子市場網(wǎng)(www.dzsc.com)
coolrunner-ii器件中的每個輸入/輸出腳都具有施密特觸發(fā)器(schmitt trigger)的功能,并可提供500 mv的磁滯范圍。該功能除了能夠有效地抑制噪聲和用于模擬信號的接收之外,還可用于rc振蕩回路,為系統(tǒng)提供靈活和廉價的時鐘信號。該功能可以通過屬性控制來使能和旁路。
(1)約束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl語言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog語言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
歡迎轉(zhuǎn)載,信息來自維庫電子市場網(wǎng)(www.dzsc.com)
(1)約束文件(ucf)
net (signal name) schmitt_trigger;
例如:
net data_in schmitt_trigger;
net clock schmitt_trigger;
(2)vhdl語言
attribute schi4itt_trigger : string;
attribute schmitt_trigger of <signal name>: signal is "true";
例如:
attribute schmitt_trigger : string;
attribute schmitt_trigger of data_in : signal is "true";
attribute schmitt_trigger of clock : signal is "true";
(3)verilog語言
//synthesis attribute schmitt_trigger of <signal name>;
例如:
//synthesis attribute schmitt_trigger of data_in;
//synthesis attribute schmitt_trigger of clock;
歡迎轉(zhuǎn)載,信息來自維庫電子市場網(wǎng)(www.dzsc.com)