問題：
　　是不是用fpga express能編譯標(biāo)準(zhǔn)的verilog hdl語言寫的程序，再生成edif文件交給max+plus處理？具體如何操作？
回答一：
　　好像max+plus也能編輯verilog hdl語言寫的程序,具體做法從文本編輯窗口輸入程序,編譯即可.
回答二：
　　還是推薦大家用synplify做綜合吧，對語法的要求不嚴(yán)格，軟件也不大。
連altera和xilinx的人都推薦我用。

回答三：
　　synplify 在綜合方面好一些,但maxplus ii 的功能更全面些,我覺得.

回答四：
　　synplify速度快，但不見得綜合效果好。leonardo spectrum不錯(cuò)，還可以綜合到asic。

回答五：
　　half and half, i don't agree the viewpoints.

回答六：
　　synplify only synthesis, mp2 including all fpga application function.their
marketing focus is not same. please advise.

回答七：
　　the web-friend advise is right if your design is not large-scale, but pls notes that altera is fpga vendor, not hdl synthesis vendor. if you think your design is very large, for example, you will design with 10k100 or acek etc, at least over 5k dff application, you should apply such as fpga express or exemplar etc tools. 

回答八：
　　the web-friend is very important, i use the synplify from 1997, it is very good, fpga express embbed their core-solution.